A novel clock gating approach for the design of low-power linear feedback shift register

This paper presents an efficient solution to reduce the power consumption of the popular linear feedback shift register by exploiting the gated clock approach. The power reduction with respect to other gated clock schemes is obtained by an efficient implementation of the logic gates and properly reducing the number of XOR gates in the feedback network. Transistor level simulations are performed by using standard cells in a 28-nm FD-SOI CMOS technology and a 300-MHz clock. Simulation results show a power reduction with respect to traditional implementations, which reaches values higher than 30%

Integrated pressure control strategies for sustainable management of water distribution networks

Pressure control in urban Water Distribution Networks (WDNs) allows to reduce water losses, delays asset deterioration and makes effective replacement works. This contribution presents an integrated approach to control pressure for leakage reduction that combines a recent strategy for optimal design of district metered areas (DMAs) with optimal setting of pressure reduction valves. DMA design strategy encompasses the possibility of reconfiguring water flows by closing some gate valves at district boundaries, while the optimal setting of PRVs driven by local or remote real time controls improves leakage reduction and reliability of final solution. The integrated approach is implemented into the WDNetXL platform for advanced WDN analysis, planning and management and is demonstrated on a real urban WDN in Southern Italy. As such, this work proposes an innovative methodology while demonstrating its transfer to water utilities and practitioners to support decisions in real-world complex scenarios

integrated pressure control strategies for sustainable management of water distribution networks

Pressure control in urban Water Distribution Networks (WDNs) allows to reduce water losses, delays asset deterioration and makes effective replacement works. This contribution presents an integrated approach to control pressure for leakage reduction that combines a recent strategy for optimal design of district metered areas (DMAs) with optimal setting of pressure reduction valves. DMA design strategy encompasses the possibility of reconfiguring water flows by closing some gate valves at district boundaries, while the optimal setting of PRVs driven by local or remote real time controls improves leakage reduction and reliability of final solution. The integrated approach is implemented into the WDNetXL platform for advanced WDN analysis, planning and management and is demonstrated on a real urban WDN in Southern Italy. As such, this work proposes an innovative methodology while demonstrating its transfer to water utilities and practitioners to support decisions in real-world complex scenarios

Progettazione di un controllore fuzzy in tecnologia CMOS con approccio a condensatore commutato

Dottorato di ricerca in ingegneria elettrotecnica. 11. ciclo. Relatore G. PalmisanoConsiglio Nazionale delle Ricerche - Biblioteca Centrale - P.le Aldo Moro, 7, Rome; Biblioteca Nazionale Centrale - P.za Cavalleggeri, 1, Florence / CNR - Consiglio Nazionale delle RichercheSIGLEITItal

Efficient Design Strategy for Optimizing the Settling Time in Three-Stage Amplifiers Including Small- and Large-Signal Behavior

An analytical criterion for the optimization of the small-signal settling time in three-stage amplifiers is carried out. The criterion is based on making equal the two exponential decays of the step response. Including slew-rate effects, a useful design strategy for the design of three-stage operational transconductance amplifier is provided. Extensive time-domain simulations on a transistor-level design in a 65-nm CMOS process confirm the validity of the proposed approach

Hybrid Full Adders: Optimized Design, Critical Review and Comparison in the Energy-Delay Space

In this paper, we design and compare seven meaningful hybrid one-bit full adders topologies that are optimized in terms of energy-delay trade-offs to operate in multibit ripple carry adders. The goal is to provide the designer with a simple and powerful approach for choosing the best topology for a given power budget, speed performance, or any combination of both. The design and comparison deal with 4-bit and 8-bit ripple carry adders and exploit the derivation of the energy-efficient curves in the energy-delay space. To do so, first we define the procedures to obtain energy consumption and propagation delay by simulating a ripple carry adder designed at a transistor level. Then, we introduce a design methodology to optimize a ripple carry adder by minimizing some significant figures-of-merit in terms of energy-delay trade-offs. The comparison of the energy-efficient curves allows us to make a simple and effective comparison as well as to identify the best one-bit full adder topologies

A gm/ID-Based Design Strategy for IoT and Ultra-Low-Power OTAs with Fast-Settling and Large Capacitive Loads

In this paper, a new strategy for the design of ultra-low-power CMOS operational transconductance amplifiers (OTAs), using the gm/ID approach, is proposed for the Internet-of-things (IoT) scenario. The strategy optimizes the speed/dissipation of the OTA in terms of settling time, including slew-rate effects. It was designed for large capacitive loads and for transistors biased in the sub-threshold region, but it is also suitable for low-capacitive loads or for transistors biased in the saturation region. To validate the proposed strategy, a well-known three-stage OTA was designed starting from capacitive load and settling time requirements. Simulations confirmed that the OTA satisfies the specifications (even under Monte Carlo analysis), thus proving the correctness of the proposed approach

Analysis and Comparison in the Energy-Delay Space of Nanometer CMOS One-Bit Full-Adders

In this paper we analyze, design and compare six significant topologies of one-bit full adders in terms of their Energy-Efficient Curves in the Energy-Delay Space. We define the simulation strategies that are adopted to make a fair comparison even among cells with very different characteristics. Each topology is designed through a methodology which, thanks to the adoption of a circuit optimizer, allows to design the circuit under different energy-delay trade-offs and to derive the Energy-Efficient Curves. The comparison of the topologies is made using a 28nm CMOS technology in terms of normalized Energy-Efficient Curves. In particular, plotting all these Energy-Efficient Curves in a single graph makes the comparison very effective and allows the designer to choose the best topology or discard the worst ones, at a glance

Hybrid Full Adders: Optimized Design, Critical Review and Comparison in the Energy-Delay Space

In this paper, we design and compare seven meaningful hybrid one-bit full adders topologies that are optimized in terms of energy-delay trade-offs to operate in multibit ripple carry adders. The goal is to provide the designer with a simple and powerful approach for choosing the best topology for a given power budget, speed performance, or any combination of both. The design and comparison deal with 4-bit and 8-bit ripple carry adders and exploit the derivation of the energy-efficient curves in the energy-delay space. To do so, first we define the procedures to obtain energy consumption and propagation delay by simulating a ripple carry adder designed at a transistor level. Then, we introduce a design methodology to optimize a ripple carry adder by minimizing some significant figures-of-merit in terms of energy-delay trade-offs. The comparison of the energy-efficient curves allows us to make a simple and effective comparison as well as to identify the best one-bit full adder topologies